The present invention relates generally to a single event upset resistant semiconductor circuit element, and more particularly to a single event upset resistant semiconductor circuit element formed of a plurality of parallel-connected semiconductor cell elements.
A single event upset (SEU) is a type of electrical disturbance that can affect microelectronic devices. SEUs have multiple causes. In one instance, an SEU may be caused by a cosmic ray striking the microelectronic device. A cosmic ray is an exceedingly high energy particle from space. Cosmic rays consist mostly of protons but may also be heavier atomic nuclei. They may have energies of a billion electron volts (more energetic than many high energy particles created on earth in the most powerful particle accelerators), and are moving at nearly the speed of light. The earth""s magnetic field deflects and its atmosphere absorbs most cosmic rays. Therefore, people and objects on the earth""s surface are not highly affected. However, they do affect spacecraft and high-flying aircraft. Spacecraft and aircraft at high latitudes are more affected due to orientation of the earth""s magnetic field.
In another instance, an SEU may be caused by an alpha particle striking the microelectronic device. Alpha particles are helium nuclei and are emitted from large atoms as a result of radioactive decay. Since the alpha particle does not contain any electrons, it has a positive charge. Alpha particles are typically present as low-level background radiation at the Earth""s surface, and occur as a result of the decay of naturally occurring radioactive isotopes. A common source of alpha particles that may affect microelectronic devices is the minute amount of radioactive isotopes present in typical packaging materials.
Neutrons are another type of energetic particles that can affect electronic devices. Energetic neutrons are produced by nuclear reactions, collisions of protons with matter or by interactions between cosmic rays and the earth""s atmosphere. Due to their lack of charge, they are able to deeply penetrate electronic devices, which can cause SEU effects in microelectronic devices.
Energetic particles th at strike microelectronic devices may adversely affect the operation of the electronic circuits. In particular, an energetic particle that hits a semiconductor memory cell element can cause the cell element to operate incorrectly, and can therefore cause the memory cell to change states (i.e., a single event upset or SEU). A memory cell corrupted by an energetic particle may cause severe problems, such as improper operation of a computer using an affected memory. For example, if a memory state change occurs in a critical memory component such as a processor program or data stack, the CPU may operate improperly after accessing the stack. It should be noted that although the effects of energetic particles on semiconductor memory cells are the most troublesome because the effect of an SEU disturbance may be xe2x80x9cheldxe2x80x9d for some time, energetic particles in other circuitry also may be problematic. For instance, if a transistor in a combinational logic device is hit by radiation at a critical time, the logic device output may be affected and the output change may cause an error, which may be propagated through any subsequent circuitry.
An SEU typically is caused by electron-hole pairs created by, and along the path of, an energetic particle as it passes through a semiconductor device such as a memory cell. If the energetic particle generates a sufficient amount of charge in a critical volume of a semiconductor circuit element, then the logic state of the semiconductor circuit element may be corrupted. Either N-channel or P-channel Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) may be upset by an energetic particle. The primary upset condition of concern is for an xe2x80x9coffxe2x80x9d device to be momentarily turned xe2x80x9conxe2x80x9d by the generated charge.
FIG. 1 shows a representative metal-oxide-semiconductor (MOS) N-channel enhancement mode MOSFET and its schematic symbol. The N-channel MOSFET has a gate terminal G, a source terminal S, and a drain terminal D. The gate controls a channel region between the source and drain such that current flows in the device when the gate voltage is sufficiently positive with respect to the source terminal. When an energetic particle xe2x80x9cRxe2x80x9d strikes the semiconductor material, it may generate electron-hole pairs as shown by the respective positive and negative symbols. As can be seen from the figure, when the energetic particle xe2x80x9cRxe2x80x9d passes through the device, it may cause regions of accumulated negative and positive charge which may mimic the affect of gate voltage. Therefore, the energetic particle may momentarily affect operation of the transistor and may cause the transistor to effectively be biased xe2x80x9conxe2x80x9d.
FIG. 2 shows a P-channel MOSFET and its schematic symbol. In contrast to the N-channel MOSFET, the P-channel MOSFET source and drain reside in an N-well, which provides electrical isolation and the appropriate semiconductor material polarity for fabrication of the complementary P-channel MOSFET co-resident with N-channel MOSFETs. As with the N-channel MOSFET, an energetic particle can affect the P-channel MOSFET and may bias the transistor xe2x80x9conxe2x80x9d. It should be noted that an energetic particle strike in the N-well region may also cause undesirable effects that result in a transistor malfunction.
N-channel and P-channel MOSFETs are used together to implement Complementary Metal Oxide Semiconductor (CMOS) circuits that are well known in the art. An example basic CMOS circuit is illustrated in FIG. 3 which shows a prior art inverter and its typical schematic symbol. The prior art inverter is composed of a P-channel MOSFET and an N-channel MOSFET connected as shown. If the input is at a high voltage level (i.e., a logic one), the P-channel MOSFET will be biased off while the N-channel MOSFET will be biased on. The P-channel MOSFET will act as essentially an open switch and the N-channel MOSFET will act as a closed switch in series with a small resistance connected to ground. Therefore the output will be a low voltage level (off, or a logic zero). Conversely, if the input is low, the P-channel MOSFET will be biased on and the N-channel will be biased off. The N-channel MOSFET will therefore act as an open switch and the P-channel MOSFET will act as a closed switch in series with a small resistance connected to VDD. The inverter output will therefore be a high voltage level (on, or a logic one). A significant benefit of the CMOS circuit topology is that in either static logic state, no current flows from VDD to ground, so the power consumption is extremely low.
FIG. 4 shows a graph of the output voltage of the prior art inverter during an SEU occurrence where the N-channel MOSFET is biased off and the output of the prior art inverter is at a high voltage level. Upon a strike by an energetic particle, the N-channel MOSFET may be momentarily biased on. The result is a condition where both MOSFETs are biased on, and a voltage division occurs, represented by FIG. 3A with both switches closed. The output voltage in the prior art inverter may swing towards about one-half of the supply voltage VDD, placing the output voltage at an indeterminate level for a period of time. Therefore, the output may change state, and may even oscillate between output states (the threshold voltage of one-half VDD is typically a decision level below which the output is a logic zero and above which the output is a logic one). This is an undesirable condition and may lead to other errors.
FIG. 5 shows a prior art memory cell formed of two inverters. A logic one on the input will be inverted twice, producing a logic one at the output. This regenerative positive feedback results in persistent storage of the input state in the circuit. Any disturbance to this memory cell that causes the stored state to be altered will appear on the output and will be persistently stored.
FIG. 6 shows a prior art master-slave D flip-flop circuit of the type that is typically implemented in a CMOS semiconductor process using N-MOSFET and P-MOSFET transistors as previously described. The circuit comprises multiple coupled inverters and transmission gates, with the transmission gates being used to gate signals responsive to specific clock levels. The output of the first pair of coupled inverters is coupled into the second pair of inverters. The action of the circuit is to capture the state of the logic signal present on the D input with the rising edge of the CLK control and to store that state persistently. An SEU occurrence in either of the coupled inverter sections may cause the stored state of the flip-flop to be changed leading to an error condition.
FIG. 7 shows a typical 1 micrometer (micron) scale MOSFET. The MOSFET includes a gate G with a pair of contacts, a source S, and a drain D. The figure shows an approximate size of an energetic particle strike region in relation to the 1 micron transistor. This size approximation is based upon the likelihood of an SEU occurrence in a 1 micron transistor as compared to the likelihood of an SEU occurrence in a 0.25 micron scale transistor. A semiconductor cell element of this size, when hit by an energetic particle, is typically not affected. Older and larger semiconductor designs were therefore inherently more SEU resistant, and could generally absorb an energetic particle strike without any state change. It can be appreciated from the figure that as the scale of individual transistors shrink, an entire transistor or multiple transistors may fall within an energetic particle strike region. The increasing miniaturization of transistors therefore leads to an increasing possibility of erroneous outputs and faulty circuit operation.
FIG. 8 shows a typical prior art P-channel MOSFET configuration wherein a number of P-channel transistors are fabricated in an N-well. This allows for a certain efficiency of physical circuit layout, as P-channel MOSFETs may be placed on the same lateral pitch as the corresponding N-channel MOSFETs to implement the coupled inverter or other circuit configurations. It is apparent from the figure that an energetic particle strike within the shared N-well may affect many transistors therein.
In memory arrays having large quantities of semiconductor circuit elements, such as a general purpose storage memory, an SEU occurrence may be detected and corrected by applying some form of error detection and correction (i.e., parity, block codes, cyclic codes, etc.). Once an error in an affected semiconductor circuit element is detected, it can be restored to an initial state by a subsequent write operation.
In an attempt to address the deficiencies of the redundant semiconductor circuit element approach, the prior art has employed a voting approach. The voting approach employs multiple semiconductor circuit elements, with a typical number of three such redundant elements. For a memory read operation, the state of each circuit element is read and compared with a majority vote of the multiple circuit elements governing the overall state of the redundant circuit. Using voting, the circuit can detect an error, and can correct it by rewriting the affected circuit element with the data determined by the other redundant circuit elements. An example prior art voting circuit is taught by McIver et al in U.S. Pat. No. 5,031,180.
A drawback of the prior art voting approach is that it requires additional logic circuitry or microprocessor attention to perform the voting function and to couple the voted result to the output of the circuit element. The additional logic circuitry will more than triple the physical size of the circuit element. The speed of the logic function of the circuit element will also be degraded by the addition of circuitry that signals must propagate through from input to output. As such, the voting process therefore increases the time required to access the memory.
Registers are small sets of memory that are repeatedly used by a CPU in order to process data. A main advantage of register memory is its generally fast access speed. A typical use is to process CPU instructions and to hold portions of general memory contents for data manipulation. Because of the need to maintain high access speeds, applying block codes to a register memory is therefore not practical. The decode logic for these block codes would unacceptably degrade the access speed.
What is needed, therefore, are improvements to semiconductor circuit elements to make them resistant to upsets caused by energetic particles.
According to a first embodiment of the invention, a single event upset resistant semiconductor circuit element includes a plurality of parallel-connected semiconductor cell elements. Each semiconductor cell element of the plurality of parallel-connected semiconductor cell elements is physically separated from a nearest semiconductor cell element of the circuit element.
According to a second embodiment of the invention, a single event upset resistant semiconductor circuit element system includes a plurality of parallel-connected semiconductor cell elements arranged in a predetermined pattern of interleaved, spaced-apart semiconductor cell elements. Any two semiconductor cell elements of one circuit element of the system have positioned there between at least one intervening semiconductor cell element of another circuit element of the system.
According to another aspect of the invention, a method of forming a single event upset resistant circuit element comprises the step of forming a first parallel-connected semiconductor cell element of the semiconductor circuit element. The method further comprises the step of forming a second parallel-connected semiconductor cell element spaced apart from the first parallel-connected semiconductor cell element. The semiconductor circuit element is formed of a plurality of spaced semiconductor cell elements.
The above and other features and advantages of the present invention will be further understood from the following description of the preferred embodiments thereof, taken in conjunction with the accompanying drawings.